As technology scales down, dense integration and high operating frequencies associated with increased number of I/O buffers are factors contributing to electromagnetic emission (EME) increase of FPGA devices. Noting that the EME depends not only on the dynamic power dissipated by the device, but also on the coupling degree between the layout of the routed tracks and the signal switching activity along with these tracks, it is of high interest and challenging to investigate FPGA EME performance. With this purpose, this paper presents an analysis about the impact of the placement and routing (P&R) process of logic inside the FPGA on the chip EME level. With this goal in mind, a softcore processor was placed and routed based on three different strategies in the configurable logic block (CLB) array of a commercial FPGA and executed an application code running over an operating system (OS). One of these P&R strategies is performed automatically by a commercial CAD tool, whose results are compared against the other two manually P&R processes of the FPGA. Two experiments have been performed. The obtained results indicate that the EME level can be affected up to 21.8% by the way the processor is placed and routed inside the FPGA. In this scenario, we suggest to improve the efficiency of the commercial CAD tool to execute the P&R process by having in mind the FPGA EME.