Gate-all-around (GAA) transistors are anticipated to have a substantial impact in achieving logic scaling in the nanometer technology node range, serving as a substitute for the current FinFET technology which lacks acceptable immunity against short channel effect at such miniaturization. GAA transistors offer several advantages over older transistor designs, such as better performance, lower leakage, and reduced energy consumption. This makes them a more sustainable and environmentally friendly alternative to current architectures. In term of integration, vertical gate-all-around devices offer extreme density capability, surpassing equivalent planar technologies. Nevertheless, the development of vertical technology requires rethinking the entire development chain from design to technology. Here, we will present an overview of this technology with a particular focus on the engineering of 3D nanostructured channels and on the integration of S/D contacts on such vertical channels.