Vertical junctionless gate-all-around nanowire transistors show excellent electrical performance and can be fabricated using a top-down approach in conventional CMOS process technology. Thinning of the nanowires to the desired diameter is obtained by sacrificial wet oxidation. Then, the gate oxide is grown by dry oxidation. These oxidation steps deeply affect the doping distribution in the nanowire due to dopant segregation and selfinterstitial injection, especially for p-type dopants. This effect is more pronounced in 3D nanostructures with respect to bulk devices, due to geometry. Modeling the resulting doping distribution is a prerequisite for understanding the electrical properties of the devices and exploring their potential for optimization. In this work, 3D TCAD process and device simulations were performed using Synopsys Sentaurus and the results are compared with experimental data of devices fabricated at CNRS-LAAS. The impact of the implemented process and device models and their capability to predict nanowire properties and device behavior is assessed.