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3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact ModelVLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩
Book section
hal-03371673v1
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1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors47th IEEE ESSDERC, Sep 2017, Leuven, Belgium. ⟨10.1109/ESSDERC.2017.8066585⟩
Conference papers
hal-01695259v1
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Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications2020
Preprints, Working Papers, ...
hal-02732902v1
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