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authFullName_s : Chhandak Mukherjee

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

Arnaud Poittevin , Chhandak Mukherjee , Ian O'Connor , Cristell Maneux , Guilhem Larrieu , et al.
VLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩
Book section hal-03371673v1

1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors

Chhandak Mukherjee , Cristell Maneux , Julien Pezard , Guilhem Larrieu
47th IEEE ESSDERC, Sep 2017, Leuven, Belgium. ⟨10.1109/ESSDERC.2017.8066585⟩
Conference papers hal-01695259v1
Image document

Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications

Ian O'Connor , Zlatan Stanojevic , Oskar Baumgartner , Chhandak Mukherjee , Guilhem Larrieu , et al.
Preprints, Working Papers, ... hal-02732902v1