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Random telegraph signals in nanoscale vertical junctionless transistor with gate-all-around

Simon Grall , Abhishek Kumar , Laurent Jalabert , Soo-Hyeon Kim , Guilhem Larrieu , et al.
Applied Physics Letters, 2022, 15 (7), pp.075001. ⟨10.35848/1882-0786/ac72f6⟩
Journal articles hal-03607609v1
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Vertical Junction-less Gate-All-Around Transistors with Reliable 3D Multilevel Contact Engineering for High Performance and Low Power Applications

Abhishek Kumar , Jonas Müller , Aurélie Lecestre , Guilhem Larrieu
2022
Preprints, Working Papers, ... hal-03600982v1
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3D logic cells design and results based on Vertical NWFET technology including tied compact model

Mukherjee Chhandak , Marina Deng , François Marc , Cristell Maneux , Arnaud Poittevin , et al.
28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020, Oct 2020, Salt Lake City (virtual), United States. ⟨10.1109/VLSI-SOC46417.2020.9344094⟩
Conference papers hal-03166674v1
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Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

Bruno Neckel Wesling , Marina Deng , Mukherjee Chhandak , Magali de Matos , Abhishek Kumar , et al.
Solid-State Electronics, 2022, 194, pp.108359. ⟨10.1016/j.sse.2022.108359⟩
Journal articles hal-03657781v1

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

Arnaud Poittevin , Chhandak Mukherjee , Ian O'Connor , Cristell Maneux , Guilhem Larrieu , et al.
VLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩
Book section hal-03371673v1