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3D logic cells design and results based on Vertical NWFET technology including tied compact model

Mukherjee Chhandak , Marina Deng , François Marc , Cristell Maneux , Arnaud Poittevin , et al.
28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020, Oct 2020, Salt Lake City (virtual), United States. ⟨10.1109/VLSI-SOC46417.2020.9344094⟩
Conference papers hal-03166674v1

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

Arnaud Poittevin , Chhandak Mukherjee , Ian O'Connor , Cristell Maneux , Guilhem Larrieu , et al.
VLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩
Book section hal-03371673v1
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Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology

Ian O'Connor , Arnaud Poittevin , Sébastien Le Beux , Alberto Bosio , Zlatan Stanojevic , et al.
EuroSOI-ULIS, Sep 2021, Caen, France. ⟨10.1109/EuroSOI-ULIS53016.2021.9560180⟩
Conference papers hal-03407210v1