Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around - LAAS - Laboratoire d'Analyse et d'Architecture des Systèmes Access content directly
Journal Articles Nanoscale Research Letters Year : 2016

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

Abstract

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires’ suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.
Fichier principal
Vignette du fichier
document(1).pdf (2.64 Mo) Télécharger le fichier
Origin : Publisher files allowed on an open archive
Loading...

Dates and versions

hal-01942311 , version 1 (26-06-2019)

Identifiers

Cite

Youssouf Guerfi, Guilhem Larrieu. Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around. Nanoscale Research Letters, 2016, 11, pp.210. ⟨10.1186/s11671-016-1396-7⟩. ⟨hal-01942311⟩
33 View
12 Download

Altmetric

Share

Gmail Facebook X LinkedIn More