Micron-to-Submicron Cu electroplating in view of Agile-X LSI Chips Fabrication using Open Facility - LAAS - Laboratoire d'Analyse et d'Architecture des Systèmes Access content directly
Conference Papers Year : 2023

Micron-to-Submicron Cu electroplating in view of Agile-X LSI Chips Fabrication using Open Facility

Abstract

The goal of the Agile-X project at UTokyo d.lab, supported by MEXT X-nics, Japan, is to produce custom logic LSI devices (real silicon) in a very short turnaround time , ideally, in one week. To achieve the goal, d.lab deploys a "structured ASIC" approach. As shown in Fig.1, the transistors and functional building blocks (such as MPU and SRAMs) are prefabricated by a mega-foundry, and only adding a couple of metal wiring layers completes an LSI device. The key process is a chip-scale "back end of the line (BEOL)" fabrication with Q-TAT in Takeda Super Clean Room (SCR), Univ. of Tokyo. Both subtractive (etching) process for wider aluminum wirings and additive (electroplating) process for narrower copper (Cu) wirings are under development. This presentation will mainly focus on Cu wiring process optimization thanks to EU-JP international engineers' cooperation.
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Dates and versions

hal-04131037 , version 1 (16-06-2023)

Identifiers

  • HAL Id : hal-04131037 , version 1

Cite

Naonobu Shimamoto, Ayako Mizushima, David Bourrier, Etsuko Ota, Akio Higo, et al.. Micron-to-Submicron Cu electroplating in view of Agile-X LSI Chips Fabrication using Open Facility. ENRIS 2023, Renatech Euronanolab, May 2023, Paris Saclay, France. ⟨hal-04131037⟩
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