The Von Neumann architecture has been the dominant philosophy behind every computing system over the past decades, consisting of a computing and a memory unit, with data being transferred in between. Over the past few years, a significant limitation of this data transfer rate, compared to the increasing processing speed and memory capacitance has led to a transferring bottleneck known as the Von Neumann bottleneck. To overcome this problem, different architectures have been evaluated in the semiconductor research community. One that has gained significant attention amongst them is the integration of a memory element on to the processing unit or vice versa, a concept referred to as Memory-in-Logic or In-memory computing, respectively [1]. In this direction, ferroelectric materials pose as a serious candidate, by storing information through different polarised states while being integrated in a transistor device. For this purpose, a wide variety of ferroelectric materials have been studied over the past decades. But it's only since 2011[2] that hafnium oxide, an already proven CMOS compatible high-k gate dielectric, has entered the stage as a promising candidate for its recently observed ferroelectric properties. The great advantage about HfO2 is that it can retain its ferroelectric properties in highly miniaturised dimensions of a few nanometres and thus, can be integrated in ultra scaled transistor technologies like Vertical 3D Gate-all-around FET, enabling to actually have memory and logic on the same cell. In this work we present, the engineering of a ferroelectric Hf-Zr doped (Hf0.5Zr0.5O2– HZO) layer for advanced 3D gate-all-around devices. We propose a detailed material integration study of the key process parameters for the stabilisation of HZO in the orthorhombic crystalline phase in which ferroelectricity is observed. Through the integration of a 10 nm layer of HZO in planar capacitors on silicon wafers, consisting of an interfacial layer of SiO2 of 1.5 nm and a capping layer of TiN, we achieve a HZO crystallisation temperature of as low as 400°C, where the orthorhombic phase has been identified in the HZO layer by GI-XRD measurements and confirmed by electrical characterization. Additionally, optimized HZO layers have been integrated in vertical nanostructures (nanowires / nanosheets) to investigate the layer’s crystallisation by TEM on such nanostructured channel configuration. Finally, the ferroelectric HZO layers have been electrically characterized (polarisation values, endurance, coercive field) for the various fabrication parameters that were implemented. This study adds crucial knowledge and fabrication expertise towards the integration of HZO in scaled 3D gate-all-around Nanowire Field Effect Transistor technology and paves the path for an innovative vertical Memory-in-Logic cell.