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Communication Dans Un Congrès Année : 2023

Thermal consideration in nanoscale gate-all-around vertical transistors

Résumé

Devolvement of high-performance logic application in sub-20 nm technology node has gained significant attention due to their improved electrostatic and thermal control. In this work, we investigate electro-thermal transport in vertical junctionless nanowire transistors (VNWFET) at cryogenic temperatures to understand thermal effects in nanoscale regime. It highlights that heat dissipation and thermal stability are more efficient compared to planar Finfet configuration.
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Dates et versions

hal-04189328 , version 1 (29-08-2023)

Identifiants

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Guilhem Larrieu, Houssem Rezgui, Abhishek Kumar, Jonas Müller, Sylvain Pelloquin, et al.. Thermal consideration in nanoscale gate-all-around vertical transistors. Silicon Nanoelectronics Workshop (SNW 2023), Jun 2023, Kyoto, Japan. pp.27-28, ⟨10.23919/SNW57900.2023.10183951⟩. ⟨hal-04189328⟩
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