Time-Efficient Read/Write Register in Crash-prone Asynchronous Message-Passing Systems - LAAS - Laboratoire d'Analyse et d'Architecture des Systèmes
Article Dans Une Revue Computing Année : 2019

Time-Efficient Read/Write Register in Crash-prone Asynchronous Message-Passing Systems

Résumé

The atomic register is one of the most basic and useful object of computing science, and its simple read-write semantics is appealing when programming distributed systems. Hence, its implementation on top of crash-prone asynchronous message-passing systems has received a lot of attention. It was shown that having a strict minority of processes that may crash is a necessary and sufficient requirement to build an atomic register on top of a crash-prone asynchronous message-passing system. This paper visits the notion of a fast implementation of an atomic register, and presents a new time-efficient asynchronous algorithm that reduces latency in many cases: a write operation always costs a round-trip delay, while a read operation costs a round-trip delay in favorable circumstances (intuitively, when it is not concurrent with a write). When designing this algorithm, the design spirit was to be as close as possible to the original algorithm proposed by Attiya, Bar-Noy, and Dolev.
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Dates et versions

hal-01784210 , version 1 (03-05-2018)

Identifiants

Citer

Achour Mostefaoui, Michel Raynal, Matthieu Roy. Time-Efficient Read/Write Register in Crash-prone Asynchronous Message-Passing Systems. Computing, 2019, 101 (1), pp.3-17. ⟨10.1007/s00607-018-0615-8⟩. ⟨hal-01784210⟩
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