Vertical Junction-less Gate-All-Around Transistors with Reliable 3D Multilevel Contact Engineering for High Performance and Low Power Applications - LAAS - Laboratoire d'Analyse et d'Architecture des Systèmes Accéder directement au contenu
Pré-Publication, Document De Travail Année : 2022

Vertical Junction-less Gate-All-Around Transistors with Reliable 3D Multilevel Contact Engineering for High Performance and Low Power Applications

Résumé

A sub-20 nm Gate-all-around (GAA) p-type silicon nanowire array-based metal oxide semiconductor field-effect transistor (MOSFET) is presented in this paper. The transistors exhibit good Ion/Ioff characteristics and allow for the full control of the short-channel effects as revealed by their low drain-induced barrier lowering (≈10 mV/V) and near-ideal subthreshold swing (≈74 mV/dec). We show that the wider the nanowire, the higher the drive current will be while on the other hand the Ion/Ioff degrades. We study the impact of the temperature variations on the static characterization of doped Junctionless GAA P-MOSFET and compare it to Schottky barrier P-MOSFET. The JunctionLessTransistor (JLT) shows a similar trend as the Schottky barrier MOSFET for their figure of merits as observed by the subthreshold slope, DIBL and threshold voltage for decreasing temperature down to 100 K.
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Dates et versions

hal-03600982 , version 1 (08-03-2022)

Identifiants

  • HAL Id : hal-03600982 , version 1

Citer

Abhishek Kumar, Jonas Müller, Aurélie Lecestre, Guilhem Larrieu. Vertical Junction-less Gate-All-Around Transistors with Reliable 3D Multilevel Contact Engineering for High Performance and Low Power Applications. 2022. ⟨hal-03600982⟩
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