Optimized algorithm to reduce the near-field measurement time on FPGA device - LAAS - Laboratoire d'Analyse et d'Architecture des Systèmes
Communication Dans Un Congrès Année : 2019

Optimized algorithm to reduce the near-field measurement time on FPGA device

Résumé

This paper presents a sequential adaptive sampling algorithm in order to reduce the measurement time of near-field scan. The originality of this approach is to use a deterministic mesh swept according to a sequential progressive adaptive algorithm that defines whether a point must be captured or not. All the proposed algorithm parameters are set according to spatial field characteristics and the measurement setup. This approach is validated on the measurement of the magnetic field produced in near-field region by a FPGA device.

Domaines

Electronique
Fichier principal
Vignette du fichier
Optimize algorithm to reduce the near field measurement time on FPGA_final.pdf (522.14 Ko) Télécharger le fichier
Origine Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-02319472 , version 1 (18-10-2019)

Identifiants

  • HAL Id : hal-02319472 , version 1

Citer

Sebastien Serpaud, Alexandre Boyer, Sonia Ben Dhia. Optimized algorithm to reduce the near-field measurement time on FPGA device. 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2019), Oct 2019, Haining, China. ⟨hal-02319472⟩
48 Consultations
50 Téléchargements

Partager

More